AT89C51RC2-3CSCM(2003) 查看數據表（PDF） - Atmel Corporation
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AT89C51RC2-3CSCM Datasheet PDF : 125 Pages
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Table 49. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
7
6
5
4
3
2
1
-
-
-
-
-
SPIH
-
Bit
Number
7
Bit
Mnemonic Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
SPI Interrupt Priority High Bit
SPIH SPIL Priority Level
2
SPIH
0
0
0
Lowest
1
1
0
1
1
Highest
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Keyboard Interrupt Priority High Bit
KB DH KBDL Priority Level
0
KBDH
0
0
0
Lowest
1
1
0
1
1
Highest
Reset Value = XXXX X000b
Not bit addressable
0
KBDH
60 AT89C51RB2/RC2
4180B–8051–04/03
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