AT89C51RB2-RLTCM 查看數據表（PDF） - Atmel Corporation
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AT89C51RB2-RLTCM Datasheet PDF : 127 Pages
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Registers
AT89C51RB2/RC2
Table 19. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
DPU
-
M0
-
3
XRS1
2
1
0
XRS0
EXTRAM
AO
Bit
Number
7
6
5
4
3
2
1
Bit
Mnemonic Description
DPU
Disable Weak Pull-up
Cleared to activate the permanent weak pull up when latch data is logical 1
Set to disactive the weak pull-up (reduce power consumption)
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Pulse Length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
M0 periods (default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock
periods.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
XRS1
XRS0
XRAM Size
XRS1 XRS0 XRAM size
0
0 256 Bytes (default)
0
1 512 Bytes
1
0 768 Bytes
1
1 1024 Bytes
EXTRAM
EXTRAM Bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
ALE Output Bit
0
AO
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
Reset Value = XX0X 00’HSB. XRAM’0b (see Table 65)
Not bit addressable
25
4180E–8051–10/06
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