ATMEGA64-16MI 查看數據表（PDF） - Atmel Corporation
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ATMEGA64-16MI
Atmel Corporation
ATMEGA64-16MI Datasheet PDF : 363 Pages
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ATmega64(L)
Table 41. Overriding Signals for Alternate Functions in PE3..PE0
Signal
Name
PE3/AIN1/OC3A
PE2/AIN0/XCK0
PE1/PDO/TXD0
PUOE 0
0
TXEN0
PUOV 0
0
0
DDOE 0
0
TXEN0
DDOV 0
0
1
PVOE OC3B ENABLE UMSEL0
TXEN0
PVOV OC3B
XCK0 OUTPUT TXD0
DIEOE 0
0
0
DIEOV 0
0
0
DI
0
XCK0 INPUT
–
AIO
AIN1 INPUT
AIN0 INPUT
–
PE0/PDI/RXD0
RXEN0
PORTE0 • PUD
RXEN0
0
0
0
0
0
RXD0
–
Alternate Functions of Port F
The Port F has an alternate function as analog input for the ADC as shown in Table 42.
If some Port F pins are configured as outputs, it is essential that these do not switch
when a conversion is in progress. This might corrupt the result of the conversion. In
ATmega103 compatibility mode Port F is input only. If the JTAG interface is enabled, the
pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a
reset occurs.
Table 42. Port F Pins Alternate Functions
Port Pin Alternate Function
PF7
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
PF6
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
PF5
ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
PF4
ADC4/TCK (ADC input channel 4 or JTAG Test Clock)
PF3
ADC3 (ADC input channel 3)
PF2
ADC2 (ADC input channel 2)
PF1
ADC1 (ADC input channel 1)
PF0
ADC0 (ADC input channel 0)
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7.
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or
Data Register (scan chains). When the JTAG interface is enabled, this pin can not be
used as an I/O pin.
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis-
ter. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
81
2490G–AVR–03/04
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