SPI Timing
Characteristics
ATmega325/3250/645/6450
Figure 129. Maximum Frequency vs. VCC (10 - 20 MHz).
16 MHz
8 MHz
Safe Operating Area
2.7V
4.5V
5.5V
See Figure 130 and Figure 131 for details.
Table 124. SPI Timing Parameters
Description
Mode
1
SCK period
Master
2
SCK high/low
Master
3
Rise/Fall time
Master
4
Setup
Master
5
Hold
Master
6
Out to SCK
Master
7
SCK to out
Master
8
SCK to out high
Master
9
SS low to out
Slave
10
SCK period
11
SCK high/low(1)
Slave
Slave
12
Rise/Fall time
Slave
13
Setup
Slave
14
Hold
Slave
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Slave
Min
4 • tck
2 • tck
10
tck
20
20 • tck
Typ
Max
See Table 67
50% duty cycle
3.6
10
10
0.5 • tsck
ns
10
10
15
1.6
µs
15
ns
10
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK > 12 MHz
2570A–AVR–09/04
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