XMEGA D4
32.15 Two-Wire Interface Characteristics
Table 32-29 describes the requirements for devices connected to the Two-Wire Interface Bus.
The Atmel AVR XMEGA Two-wire interface meets or exceeds these requirements under the
noted conditions. Timing symbols refer to Figure 32-7.
Figure 32-7. Two-Wire Interface bus timing.
tof
tHIGH
tLOW
tr
SCL
tSU;STA
SDA
tHD;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Table 32-29. Two-wire interface characteristics.
Symbol Parameter
VIH
Input high voltage
VIL
Input low voltage
Vhys
Hysteresis of schmitt trigger inputs
VOL
Output low voltage
tr
Rise time for both SDA and SCL
tof
Output fall time from VIHmin to VILmax
tSP
Spikes suppressed by input filter
II
Input current for each I/O pin
CI
Capacitance for each I/O pin
fSCL
SCL clock frequency
RP
Value of pull-up resistor
Condition
3mA, sink current
10pF < Cb < 400pF (2)
0.1VCC < VI < 0.9VCC
fPER (3)>max(10fSCL, 250kHz)
fSCL ≤ 100kHz
fSCL > 100kHz
Min.
0.7VCC
0.5
0.05VCC (1)
0
20+0.1Cb (1)(2)
20+0.1Cb (1)(2)
0
-10
0
V----C----C----–-----0---.--4----V--
3mA
Typ.
Max.
VCC+0.5
0.3×VCC
Units
V
0.4
300
250
ns
50
10
µA
10
pF
400
kHz
1----0---0----n---s-
Cb
Ω
3----0---0----n---s-
Cb
83
8135L–AVR–06/12