C8051F045 查看數據表（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

12. CIP-51 Microcontroller

The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the

MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-

ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are

five 16-bit counter/timers (see description in Section 23), two full-duplex UARTs (see description in Sec-

tion 21 and Section 22), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address

space (see Section 12.2.6), and 8/4 byte-wide I/O Ports (see description in Section 17). The CIP-51 also

includes on-chip debug hardware (see description in Section 25), and interfaces directly with the MCUs'

analog and digital subsystems providing a complete data acquisition or control-system solution in a single

integrated circuit.

The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as

additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram).

The CIP-51 includes the following features:

- Fully Compatible with MCS-51 Instruction Set

- 25 MIPS Peak Throughput with 25 MHz Clock

- 0 to 25 MHz Clock Frequency

- 256 Bytes of Internal RAM

- 8/4 Byte-Wide I/O Ports

- Extended Interrupt Handler

- Reset Input

- Power Management Modes

- On-chip Debug Logic

- Program and Data Memory Security

DATA BUS

ACCUMULATOR

TMP1

TMP2

PSW

ALU

B REGISTER

STACK POINTER

SRAM

ADDRESS

REGISTER

SRAM

(256 X 8)

DATA BUS

BUFFER

D8

DATA POINTER

D8

PC INCREMENTER

SFR_ADDRESS

SFR

SFR_CONTROL

D8

BUS

SFR_WRITE_DATA

INTERFACE

SFR_READ_DATA

PROGRAM COUNTER (PC)

PRGM. ADDRESS REG.

RESET

CLOCK

CONTROL

LOGIC

PIPELINE

STOP

IDLE

POWER CONTROL

REGISTER

D8

D8

MEM_ADDRESS

MEM_CONTROL

MEMORY

A16

INTERFACE MEM_WRITE_DATA

MEM_READ_DATA

D8

INTERRUPT

INTERFACE

D8

SYSTEM_IRQs

DEBUG_IRQ

Figure 12.1. CIP-51 Block Diagram

Rev. 1.5

127

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