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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

22. UART1

UART1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.

Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details

in Section “22.1. Enhanced Baud Rate Generation” on page 278). Received data buffering allows

UART1 to start reception of a second incoming data byte before software has finished reading the previous

data byte.

UART1 has two associated SFRs: Serial Control Register 1 (SCON1) and Serial Data Buffer 1 (SBUF1).

The single SBUF1 location provides access to both transmit and receive registers. Reading SBUF1

accesses the buffered Receive register; writing SBUF1 accesses the Transmit register.

With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in

SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not

cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually

by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive

complete).

SFR Bus

Write to

SBUF1

TB81

SET

D

Q

CLR

SBUF1

(TX Shift)

Zero Detector

Stop Bit

Start

Tx Clock

Shift

Tx Control

Data

Send

Tx IRQ

TX1

Crossbar

UART1 Baud

Rate Generator

SCON1

TI1

Serial

Port

Interrupt

RI1

Port I/O

Rx Clock

Start

Shift

Rx IRQ

Rx Control

0x1FF RB81

Load

SBUF1

Input Shift Register

(9 bits)

Load SBUF1

SBUF1

(RX Latch)

Read

SBUF1

SFR Bus

RX1

Crossbar

Figure 22.1. UART1 Block Diagram

Rev. 1.5

277

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