C8051F317 查看數據表（PDF） - Silicon Laboratories

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C8051F317

8/16 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F310/1/2/3/4/5/6/7

SFR Definition 10.3. FLSCL: Flash Scale

R/W

FOSE

Bit7

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

0xB6

Bits7:

Bits6–0:

FOSE: Flash One-shot Enable

This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash

sense amps are enabled for a full clock cycle during Flash reads. At system clock frequen-

cies below 10 MHz, disabling the Flash one-shot will increase system power consumption.

0: Flash one-shot disabled.

1: Flash one-shot enabled.

RESERVED. Read = 0. Must Write 0.

114

Rev. 1.6

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