C8051F334 查看數據表（PDF） - Silicon Laboratories

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C8051F334

Mixed-Signal ISP Flash MCU

Silicon Laboratories 

C8051F330/1/2/3/4/5

SFR Definition 10.2. RSTSRC: Reset Source

R

R

R/W

R/W

R

R/W

R/W

R

Reset Value

-

FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Variable

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xEF

Note: Do not use read-modify-write operations (ORL, ANL) on this register.

Bit7:

Bit6:

Bit5:

Bit4:

Bit3:

Bit2:

Bit1:

Bit0:

UNUSED. Read = 0. Write = don’t care.

FERROR: Flash Error Indicator.

0: Source of last reset was not a Flash read/write/erase error.

1: Source of last reset was a FlashFlash read/write/erase error.

C0RSEF: Comparator0 Reset Enable and Flag.

0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset

source.

1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source

(active-low).

SWRSF: Software Reset Force and Flag.

0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.

1: Read: Source of last was a write to the SWRSF bit. Write: Forces a system reset.

WDTRSF: Watchdog Timer Reset Flag.

0: Source of last reset was not a WDT timeout.

1: Source of last reset was a WDT timeout.

MCDRSF: Missing Clock Detector Flag.

0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing

Clock Detector disabled.

1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock

Detector enabled; triggers a reset if a missing clock condition is detected.

PORSF: Power-On Reset Force and Flag.

This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the VDD

monitor as a reset source. Note: writing ‘1’ to this bit before the VDD monitor is enabled

and stabilized may cause a system reset. See register VDM0CN (SFR Definition 10.1)

0: Read: Last reset was not a power-on or VDD monitor reset. Write: VDD monitor is not a

reset source.

1: Read: Last reset was a power-on or VDD monitor reset; all other reset flags 

indeterminate. Write: VDD monitor is a reset source.

PINRSF: HW Pin Reset Flag.

0: Source of last reset was not RST pin.

1: Source of last reset was RST pin.

Rev. 1.7

101

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