C8051F38B-GMR 查看數據表（PDF） - Silicon Laboratories
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C8051F38B-GMR Datasheet PDF : 321 Pages
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C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.9. FRAMEL: USB0 Frame Number Low
Bit
7
6
5
4
3
2
1
0
Name
FRMEL[7:0]
Type
R
Reset
0
0
0
0
0
0
0
0
USB Register Address = 0x0C
Bit Name
Function
7:0 FRMEL[7:0] Frame Number Low Bits.
This register contains bits 7-0 of the last received frame number.
USB Register Definition 21.10. FRAMEH: USB0 Frame Number High
Bit
7
6
5
4
3
2
1
0
Name
FRMEH[2:0]
Type
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
USB Register Address = 0x0D
Bit Name
7:3 Unused Read = 00000b. Write = don’t care.
Function
2:0 FRMEH[2:0] Frame Number High Bits.
This register contains bits 10-8 of the last received frame number.
21.8. Interrupts
The read-only USB0 interrupt flags are located in the USB registers shown in USB Register
Definition 21.11 through USB Register Definition 21.13. The associated interrupt enable bits are located in
the USB registers shown in USB Register Definition 21.14 through USB Register Definition 21.16. A USB0
interrupt is generated when any of the USB interrupt flags is set to 1. The USB0 interrupt is enabled via the
EIE1 SFR (see Section “16. Interrupts” on page 118).
Important Note: Reading a USB interrupt flag register resets all flags in that register to 0.
186
Rev. 1.4
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