CS4351(2004) 查看數據表（PDF） - Cirrus Logic

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CS4351
(Rev.:2004)

192 kHz Stereo DAC with 2 Vrms Line Out

Cirrus Logic 

CS4351

6.7 Misc Control - Register 08h

7

PDN

1

6

CPEN

0

5

FREEZE

0

4

Reserved

0

3

Reserved

0

2

Reserved

0

1

Reserved

0

0

Reserved

0

6.7.1 POWER DOWN (PDN) BIT 7

Function:

When set to 1 (default) the entire device will enter a low-power state and the contents of the control reg-

isters will be retained. The power-down bit defaults to ‘1’ on power-up and must be disabled before normal

operation in Control Port mode can occur. This bit is ignored if CPEN is not set.

6.7.2 CONTROL PORT ENABLE (CPEN) BIT 6

Function:

This bit is set to 0 by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode

can be accessed by setting this bit to 1. This will allow operation of the device to be controlled by the reg-

isters and the pin definitions will conform to Control Port Mode.

6.7.3 FREEZE CONTROLS (FREEZE) BIT 5

Function:

When set to 1, this function allows modifications to be made to the registers without the changes taking

effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect

simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

When set to 0 (default), register changes take effect immediately.

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DS566PP2

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