CRD44800-ST-FB 查看數據表（PDF） - Cirrus Logic
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CRD44800-ST-FB Datasheet PDF : 76 Pages
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CS44600
1. Convert the decimal integer to binary. This is MSTR_IVOL[7:0].
2. Select the bit representation of the desired 0.25 fractional increment. This is MSTR_FVOL[1:0].
3. Concatenate MSTR_IVOL[7:0]: MSTR_FVOL[1:0] to form a 10-bit binary value.
4. Perform a 2’s complement conversion on all 10 bits.
The upper 8 bits are now the new MSTR_FVOL[7:0] and the two lower bits are MSTR_FVOL[1:0].
To convert from a 2’s complement integer:fraction value to a negative decimal, do the following:
1. Concatenate MSTR_IVOL[7:0]: MSTR_FVOL[1:0] to form a 10-bit binary value.
2. Perform a 2’s complement conversion on all 10 bits.
3. Convert the 10-bit binary number to a decimal value.
4. Divide the decimal value by 4.
MSTR_IVOL[7:0]
0001 1000
0001 0111
0000 0001
0000 0001
0000 0000
0000 0000
1111 1111
1111 1111
1111 1110
1111 1101
1000 0010
1000 0001
1000 0001
MSTR_FVOL(1:0)
00
10
11
00
01
00
10
00
11
10
00
11
00
Volume Setting
+24.00 dB
+23.50 dB
+1.75 dB
+1.00 dB
+0.25 dB
0 dB
-0.50 dB
-1.00 dB
-1.25 dB
-2.50 dB
-126.00 dB
-126.25 dB
-127.00 dB
Table 7. Master Fractional Volume Settings
56
DS633F1
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