CS4952 查看數據表（PDF） - Cirrus Logic

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CS4952

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4952/53

VSYNC will transition low to begin field one and

will remain low for 2.5 lines or (864 x 2.5) 2160

pixel cycles. Digital video input is expected to be

delivered to the CS4952/3 V [7:0] pins for 287

lines beginning on active video line 24 and continu-

ing through line 310.

Field two begins with VSYNC transitioning low

after 312.5 lines from the beginning of field one.

VSYNC stays low for 2.5 lines times and transi-

tions high with the beginning of line 315. Video in-

put on the V [7:0] pins is expected between line 336

through line 622.

Progressive Scan

The CS4952/3 supports a progessive scan mode

where the video output is non-interlaced. This is

accomplished by displaying only the first video

field for NTSC or PAL. To preserve exact MPEG-2

frame rates of 30 and 25 per second, the CS4952/3

displays the same first field repetitively but alter-

nately varies the field times. Other digital video en-

coders commonly support progressive scan by

repetitively displaying a 262 line field (524/525

lines for NTSC). In the long run this method is

flawed in that over time, the output display rate will

overrun a system clock locked MPEG-2 decom-

pressor and display a field twice every 8.75 sec-

onds.

PAL Progressive Scan

VSYNC will transistion low to begin field one and

will remain low for for 2.5 lines or (864 x 2.5) 2160

pixel times. Please reference Figure 11 for PAL

non-interlaced timing. Digital video input is ex-

pected to be delivered to the CS4952/3 V [7:0] pins

for 288 lines beginning on active video line 23 and

continuing through line 309.

Field two begins with VSYNC transitioning low

after 312 lines from the beginning of field one.

VSYNC stays low for 2.5 line times and transitions

high during the middle of line 315. Video input on

the V [7:0] pins is expected between line 335

through line 622. Field two is 313 lines long while

field one is 312.

NTSC Progressive Scan

VSYNC will transition low at line 4 to begin field

one and will remain low for 3 lines or (858 x 3)

2574 pixel times. Please reference Figure 12 for

NTSC interlaced timing. Digital video input is ex-

pected to be delivered to the CS4952/3 V [7:0] pins

for 240 lines beginning on active video line 22 and

continuing through line 261.

Field two begins with VSYNC transitioning low at

line 266. VSYNC stays low for 2.5 line times and

transitions high during the middle of line 268. Vid-

eo input on the V [7:0] pins is expected between

line 284 through line 524. Field two is 263 lines

long while field one is 262.

CCIR-656

The CS4952/3 supports an additional Slave Mode

feature that is selectable through the CCIR601 bit

of the CONTROL_0 register. The CCIR-656 slave

feature is unique because the horizontal and verti-

cal timing and digital video are combined into a

single 8-bit 27 MHz input. With CCIR-656 there

are no horizontal and vertical input or output

strobes, only 8-bit 27 MHz active CbYCrY data

with start and end of video codes being implement-

ed with reserved 00 and FF code sequences within

the video feed. As with all modes, V [7:0] are sam-

pled with the rising edge of CLK. The CS4952/3

expects the digital CCIR-656 stream to be error

free. The FIELD output toggles as with non

CCIR-656 input. CCIR-656 input timing is illus-

trated in Figure 13.

DS223PP2

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