CS495303 查看數據表（PDF） - Cirrus Logic
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CS495303 Datasheet PDF : 36 Pages
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.15 Switching Characteristics — Parallel Control Port - Motorola® Slave Mode
Parameter
Symbol Min
Max Unit
Address setup before PCP_CS and PCP_DS low
Address hold time after PCP_CS and PCP_DS low
tmas
5
tmah
5
-
ns
-
ns
Read
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS# low
tmcdr
0
-
ns
Data valid after PCP_CS and PCP_DS low with PCP_R/W high
tmdd
-
19 ns
PCP_CS and PCP_DS low for read
tmrpw
24
-
ns
Data hold time after PCP_CS or PCP_DS high after read
tmdhr
8
-
ns
Data high-Z after PCP_CS or PCP_DS high after read
tmdis
-
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
tmrd
30
read1
18 ns
-
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next tmrdtw 30
write1
-
ns
Y PCP_RW rising to PCP_IRQ falling
tmrwirqh
-
12 ns
Write
R Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
tmcdw
0
-
ns
Data setup before PCP_CS or PCP_DS high
A PCP_CS and PCP_DS low for write
PCP_R/W setup before PCP_CS AND PCP_DS low
IN PCP_R/W hold time after PCP_CS or PCP_DS high
Data hold after PCP_CS or PCP_DS high
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with
PCP_R/W high for next read1
tmdsu
8
tmwpw 24
tmrwsu 24
tmrwhld
8
tmdhw
8
tmwtrd
30
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
IM PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next tmwd
30
write1
-
ns
PCP_RW rising to PCP_BSY falling
tmrwbsyl
-
2*DCLKP + 20 -
ns
L 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing
the input data buffer. AN288 CS4953xx/CS497xxx Firmware User’s Manual should be consulted for the firmware
PRE speed limitations.
20
Copyright 2009 Cirrus Logic
DS705PP6
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