CS5550-IS 查看數據表（PDF） - Cirrus Logic
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CS5550-IS Datasheet PDF : 24 Pages
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CS5550
4.1.7 Register Read/Write
B7 B6 B5 B4 B3 B2 B1 B0
0 W/R RA4 RA3 RA2 RA1 RA0 0
The Read/Write command informs the state machine that a register access is required. During a read operation, the
addressed register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the
data is clocked into the input buffer and, and all 24 bits are transferred to the addressed register on the 24th SCLK.
W/R
Write/Read control
0 = Read register
1 = Write register
RA[4:0]
Register address bits (bits 1 through 5) of the read/write command.
Address
0
1
2
3
2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RA[4-0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Abbreviation
Config
AIN1DCoff
AIN1gn
AIN2DCoff
AIN2gn
Cycle Count
Res
OUT1
OUT2
Res
Res
FILT1
FILT2
Res
Res
Status
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Mask
Res
Ctrl
Res
Res
Res
Name/Description
Configuration Register
AIN1 Offset Register
AIN1 Gain Register
AIN2 Offset Register
AIN2 Gain Register
Number of A/D conversions used in one computation cycle (N)).
Reserved †
AIN1 Output Register
AIN2 Output Register
Reserved †
Reserved †
Computed Filtered value for AIN1
Computed Filtered value for AIN2
Reserved †
Reserved †
Status Register
Reserved
Reserved
Reserved †
Reserved
Reserved †
Reserved †
Reserved †
Reserved †
Reserved †
Reserved †
Mask Register
Reserved †
Control Register
Reserved †
Reserved †
Reserved †
† These registers are for internal use only. For proper device operation, the user must not attempt to write
to these registers.
DS630F1
17
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