CS8900A-CQZ 查看數據表（PDF） - Cirrus Logic
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CS8900A-CQZ Datasheet PDF : 138 Pages
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CS8900A
Crystal LAN™ Ethernet Controller
BufCFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides the
host with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over (by inter-
rupting at 200h, the host has an additional 512 counts before TxCOL actually overflows). The TxCOL counter is
cleared when read.
010010
These bits provide an internal address used by the CS8900A to identify this as the Transmit
Collision Counter. When reading this register, these bits will be 010010, where the LSB corre-
sponds to Bit 0.
ColCount
The upper ten bits contain the number of collisions.
Reset value is: 0000 0000 0001 0010
4.4.16 Register 13: Line Control
(LineCTL, Read/Write, Address: PacketPage base + 0112h)
7
SerTxOn
F
6
5
4
3
2
SerRxON
010011
E
D
C
B
A
LoRx Squelch 2-part DefDis PolarityDis Mod BackoffE
1
0
9
Auto AUI/10BT
8
AUIonly
LineCTL determines the configuration of the MAC engine and physical interface.
010011
These bits provide an internal address used by the CS8900A to identify this as the Line Control
Register.
SerRxON
When set, the receiver is enabled. When clear, no incoming packets pass through the receiver.
If SerRxON is cleared while a packet is being received, reception is completed and no subse-
quent receive packets are allowed until SerRxON is set again.
SerTxON
When set, the transmitter is enabled. When clear, no transmissions are allowed. If SerTxON is
cleared while a packet is being transmitted, transmission is completed and no subsequent
packets are transmitted until SerTxON is set again.
AUIonly
Bits 8 and 9 are used to select either the AUI or the 10BASE-T interface according to the fol-
lowing: [Note: 10BASE-T transmitter will be inactive even when selected unless link pulses are
detected or bit DisableLT (register 19) is set.
AUIonly (Bit 8)
AutoAUI/10BT (Bit 9)
Physical Interface
AutoAUI/10BT
ModBackoffE
PolarityDis
62
1
N/A
0>
0
0
1
AUI
0BASE-T
Auto-Select
See AUIonly (Bit 8) description above.
When clear, the ISO/IEC standard backoff algorithm is used (see Section 3.9 on page 29).
When set, the Modified Backoff algorithm is used. (The Modified Backoff algorithm extends the
backoff delay after each of the first three Tx collisions.)
The 10BASE-T receiver automatically determines the polarity of the received signal at the
RXD+/RXD- input (see Section 3.11 on page 36). When this bit is clear, the polarity is correct-
ed, if necessary. When set, no effort is made to correct the polarity. This bit is independent of
the PolarityOK bit (Register 14, LineST, Bit C), which reports whether the polarity is normal or
reversed.
CIRRUS LOGIC PRODUCT DATASHEET
DS271F4
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