CS8952(2001) 查看數據表（PDF） - Cirrus Logic
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CS8952 Datasheet PDF : 82 Pages
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CS8952
6.19 10BASE-T Status Register - Address 1Bh
15
14
13
12
11
Reserved
7
6
5
4
3
Reserved
10
Polarity OK
2
9
10BASE-T
Serial
1
8
Reserved
0
BIT
NAME
15:11 Reserved
10 Polarity OK
9
10BASE-T Serial
8:0 Reserved
TYPE
RESET
DESCRIPTION
Read Only 0 0000
Read Only 0
When high, the polarity of the receive signal (at the
RXD+/RXD- inputs) is correct. If clear, the polarity is
reversed. If the Polarity Disable bit of 10BASE-T
Configuration Register (address 1Ch) is clear, then
the polarity is automatically corrected, if needed. The
Polarity OK status bit shows the true state of the
incoming polarity independent of the Polarity Disable
bit.
Read/Write Reset to the value When set, this bit selects 10BASE-T serial mode.
on the 10BT_SER When low, this bit selects 10BASE-T nibble mode.
pin.
This bit will only affect the CS8952 if it has been con-
figured for 10 Mb/s operation.
Read Only 0 0000 0000
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
61
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