CS98100
4. MEMORY MAP AND REGISTERS
4.1 Processor Memory Map
The CS98100 externally supports up to 32 Mbytes DRAM and 16 Mbytes ROM/NVRAM. Table 9 lists
the memory map as viewed by the RISC processor, and identifies whether each segment is mapped or
cacheable.
Processor byte address
Description
0000_0000 – 07FF_FFFF
DRAM (mapped)
8000_0000 - 81FF_FFFF
DRAM (32 Mbytes)
9400_0000 – 9CFF_FFFF
16 bit NVRAM write (16 Mbytes)
9C00_0000 – 9CFF_FFFF
16 bit NVRAM/ROM (16 Mbytes)
9D00_0000 – 9DFF_FFFF
8 bit NVRAM/ROM (16 Mbytes)
A000_0000 – A1FF_FFFF
DRAM (32 Mbytes)
B000_0000 – B003_FFFF
Internal I/O (256 Kbytes)
B400_0000 – BCFF_FFFF
16 bit NVRAM write (16 Mbytes)
BC00_0000 – BCFF_FFFF
16 bit NVRAM/ROM (16 Mbytes)
BD00_0000 – BDFF_FFFF
8 bit NVRAM/ROM (16 Mbytes)
C000_0000 – FFFF_FFFF
DRAM (mapped)
Table 9. Memory Map - RISC Processor
4.2 Host Port Memory Map
Table 10 lists the memory map as viewed by host slave port.
Cacheable
Y
Y
N
Y
Y
N
N
N
N
N
Y
Host byte address
Description
0000 0000 – 003F FFFF
Internal I/O Space
1000 0000 – 13FF FFFF
DRAM space (16 Mbytes)
1400 0000 – 17FF FFFF
NVRAM space (16 Mbytes)
Table 10. Host Port Memory Map
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