JS28F320J3C-115 查看數據表（PDF） - Intel

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JS28F320J3C-115

Intel StrataFlash® Memory (J3)

Intel 

256-Mbit J3 (x8/x16)

Figure 22. Block Erase Flowchart

Start

Issue Single Block Erase

Command 20H, Block

Address

Write Confirm D0H

Block Address

Read

Status Register

SR.7 =

0

No

Suspend Erase

Yes

Bus

Operation

Command

Comments

Write

Write (Note 1)

Read

Standby

Erase Block

Erase

Confirm

Data = 20H

Addr = Block Address

Data = D0H

Addr = X

Status register data

With the device enabled,

OE# low updates SR

Addr = X

Check SR.7

1 = WSM Ready

0 = WSM Busy

1. The Erase Confirm byte must follow Erase Setup.

This device does not support erase queuing. Please see

Application note AP-646 For software erase queuing

compatibility.

Full status check can be done after all erase and write

sequences complete. Write FFH after the last operation to

reset the device to read array mode.

Suspend

Erase Loop

1

Full Status

Check if Desired

Erase Flash

Block(s) Complete

0606_09

Datasheet

63

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