FDC37C672 查看數據表（PDF） - SMSC -> Microchip
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FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
CLOCKI
t1
t2
t2
Figure 21.6 - Input Clock Timing
NAME
t1
t2
t1
t2
DESCRIPTION
Clock Cycle Time for 14.318MHZ
Clock High Time/Low Time for 14.318MHz
Clock Cycle Time for 32KHZ
Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
MIN TYP
70
35
31.25
16.53
MAX
5
UNITS
ns
ns
µs
µs
ns
t4
RESET_DRV
Figure 21.7 - Reset Timing
NAME
DESCRIPTION
t4 RESET width (Note 21.12)
MIN TYP MAX UNITS
1.5
µs
Note 21.12 The RESET width is dependent upon the processor clock. The RESET must be active while the clock is
running and stable.
SMSC FDC37C672
Page 151
DATASHEET
Rev. 10-29-03
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