ST92F124V2TC 查看數據表（PDF） - STMicroelectronics

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ST92F124V2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

WAKE-UP MASK REGISTER HIGH (WUMRH)

R250 - Read/Write

Register Page: 57

Reset Value: 0000 0000 (00h)

WAKE-UP MASK REGISTER LOW (WUMRL)

R251 - Read/Write

Register Page: 57

Reset Value: 0000 0000 (00h)

7

0

7

0

WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 WUM8

WUM7 WUM6 WUM5 WUM4 WUM3 WUM2 WUM1 WUM0

Bit 7:0 = WUM[15:8]: Wake-Up Mask bits.

If WUMx is set, an interrupt on channel INTD1

and/or a wake-up event (depending on ID1S and

WKUP-INT bits) are generated if the correspond-

ing WUPx pending bit is set. More precisely, if

WUMx=1 and WUPx=1 then:

– If ID1S=1 and WKUP-INT=1 then an interrupt on

channel INTD1 and a wake-up event are gener-

ated.

– If ID1S=1 and WKUP-INT=0 only an interrupt on

channel INTD1 is generated.

If WUMx is reset, no wake-up events can be gen-

erated.

Bit 7:0 = WUM[7:0]: Wake-Up Mask bits.

If WUMx is set, an interrupt on channel INTD1

and/or a wake-up event (depending on ID1S and

WKUP-INT bits) are generated if the correspond-

ing WUPx pending bit is set. More precisely, if

WUMx=1 and WUPx=1 then:

– If ID1S=1 and WKUP-INT=1 then an interrupt on

channel INTD1 and a wake-up event are gener-

ated.

– If ID1S=1 and WKUP-INT=0 only an interrupt on

channel INTD1 is generated.

If WUMx is reset, no wake-up events can be gen-

erated.

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