ST92250JDV2TC 查看數據表（PDF） - STMicroelectronics

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ST92250JDV2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

6.3 DMA TRANSACTIONS

The purpose of an on-chip DMA channel is to

transfer a block of data between a peripheral and

the Register File, or Memory. Each DMA transfer

consists of three operations:

– A load from/to the peripheral data register to/

from a location of Register File (or Memory) ad-

dressed through the DMA Address Register (or

Register pair)

– A post-increment of the DMA Address Register

(or Register pair)

– A post-decrement of the DMA transaction coun-

ter, which contains the number of transactions

that have still to be performed.

If the DMA transaction is carried out between the

peripheral and the Register File (Figure 57), one

register is required to hold the DMA Address, and

one to hold the DMA transaction counter. These

two registers must be located in the Register File:

the DMA Address Register in the even address

register, and the DMA Transaction Counter in the

next register (odd address). They are pointed to by

the DMA Transaction Counter Pointer Register

(DCPR), located in the peripheral’s paged regis-

ters. In order to select a DMA transaction with the

Register File, the control bit DCPR.RM (bit 0 of

DCPR) must be set.

If the transaction is made between the peripheral

and Memory, a register pair (16 bits) is required

for the DMA Address and the DMA Transaction

Counter (Figure 58). Thus, two register pairs must

be located in the Register File.

The DMA Transaction Counter is pointed to by the

DMA Transaction Counter Pointer Register

(DCPR), the DMA Address is pointed to by the

DMA Address Pointer Register (DAPR),both

DCPR and DAPR are located in the paged regis-

ters of the peripheral.

Figure 57. DMA Between Register File and Peripheral

IDCR

IVR

DAPR

DCPR

DATA

PERIPHERAL

PAGED REGISTERS

FFh

PAGED

REGISTERS

F0h

EFh

SYSTEM

REGISTERS

E0h

DFh

END OF BLOCK

INTERRUPT

SERVICE ROUTINE

000100h

000000h

ISR ADDRESS

MEMORY

VECTOR

TABLE

DMA

TABLE

122/429

9

DATA

ALREADY

TRANSFERRED

DMA

COUNTER

DMA

ADDRESS

REGISTER FILE

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