ST92250DV2TC 查看數據表（PDF） - STMicroelectronics

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ST92250DV2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)

EXTERNAL MEMORY SIGNALS (Cont’d)

8.2.8 WAIT: External Memory Wait

WAIT (Alternate Function Input, Active low) indi-

cates to the ST9 that the external memory requires

more time to complete the memory access cycle. If

bit EWEN (EIVR) is set, the WAIT signal is sam-

pled with the rising edge of the processor internal

clock during phase T1 or T2 of every memory cy-

cle. If the signal was sampled active, one more in-

ternal clock cycle is added to the memory cycle.

On the rising edge of the added internal clock cy-

cle, WAIT is sampled again to continue or finish

the memory cycle stretching. Note that if WAIT is

sampled active during phase T1 then AS is

stretched, while if WAIT is sampled active during

phase T2 then DS is stretched. WAIT is enabled

via software as the Alternate Function input of the

associated I/O port bit (refer to specific ST9 ver-

sion to identify the specific port and pin). Refer to

Figure 78.

Figure 78. External memory Read/Write sequence with external wait request (WAIT pin)

T1

T2

T1

T2

T1

T2

WAIT

SYSTEM

CLOCK

P1, P9

AS (MC=0)

ALE (MC=1)

DS (MC=0)

ADDRESS

ADDRESS

ADDRESS

P0

ADD.

D.IN

ADDRESS

D.IN

ADD.

D.IN

RW (MC=0)

OEN (MC=1)

WEN (MC=1)

P0

ADD. D.OUT

RW (MC=0)

OEN (MC=1)

WEN (MC=1)

ADDRESS

D.OUT ADD.

DATA OUT

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