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ST92150CR1TC 查看數據表(PDF) - STMicroelectronics

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ST92150CR1TC Datasheet PDF : 429 Pages
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I2C BUS INTERFACE
10.8 I2C BUS INTERFACE
10.8.1 Introduction
The I2C bus Interface serves as an interface be-
tween the microcontroller and the serial I2C bus. It
provides both multimaster and slave functions with
both 7-bit and 10-bit address modes; it controls all
I2C bus-specific sequencing, protocol, arbitration,
timing and supports both standard (100KHz) and
fast I2C modes (400KHz).
Using DMA, data can be transferred with minimum
use of CPU time.
The peripheral uses two external lines to perform
the protocols: SDA, SCL.
Interrupt Features:
Interrupt generation on error condition, on
transmission request and on data received
Interrupt address vector for each interrupt
source
Pending bit and mask bit for each interrupt
source
Programmable interrupt priority respects the
other peripherals of the microcontroller
Interrupt address vector programmable
10.8.2 Main Features
Parallel-bus/I2C protocol converter
Multi-master capability
7-bit/10-bit Addressing
Standard I2C mode/Fast I2C mode
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
Interrupt generation on error conditions
Interrupt generation on transfer request and on
data received
DMA Features:
DMA both in transmission and in reception with
enabling bits
DMA from/toward both Register File and
Memory
End Of Block interrupt sources with the related
pending bits
I2C Master Features:
Start bit detection flag
Clock generation
I2C bus busy flag
Arbitration Lost flag
End of byte transmission flag
Transmitter/Receiver flag
Stop/Start generation
I2C Slave Features:
Stop bit detection
I2C bus busy flag
Detection of misplaced start or stop condition
Programmable I2C Address detection (both 7-
bit and 10-bit mode)
General Call address programmable
Transfer problem detection
End of byte transmission flag
Transmitter/Receiver flag.
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