ST92250JDV2QB 查看數據表（PDF） - STMicroelectronics

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ST92250JDV2QB

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

10-BIT ANALOG TO DIGITAL CONVERTER (ADC)

REGISTER DESCRIPTION (Cont’d)

Bit 5 = ECI: End of Conversion Interrupt Enable.

This bit masks the End of Conversion interrupt re-

quest.

0: Mask End of Conversion interrupts

1: Enable End of Conversion interrupts

Bit 4 = AWDI: Analog Watchdog Interrupt Enable.

This bit masks or enables the Analog Watchdog

interrupt request.

0: Mask Analog Watchdog interrupts

1: Enable Analog Watchdog interrupts

Bit 3 = Reserved.

INTERRUPT VECTOR REGISTER (AD_IVR)

R255 - Read/Write

Register Page: 63

Reset Value: xxxx xx10 (x2h)

7

0

V7 V6 V5 V4 V3 V2 W1 0

Bits 7:2 = V[7:2]: ADC Interrupt Vector.

This vector should be programmed by the user to

point to the first memory location in the Interrupt

Vector table containing the starting addresses of

the ADC interrupt service routines.

Bits 2:0 = PL[2:0]: ADC Interrupt Priority Level.

These three bits are used to select the Interrupt

priority level for the ADC.

Bit 1 = W1: Word Select.

This bit is set and cleared by hardware, according

to the ADC interrupt source.

0: Interrupt source is the Analog Watchdog, point-

ing to the lower word of the ADC interrupt serv-

ice block (defined by V[7:2]).

1:Interrupt source is the End of Conversion inter-

rupt, thus pointing to the upper word.

Note: When two requests occur simultaneously,

the Analog Watchdog Request has priority over

the End of Conversion request, which is held

pending.

Bit 0 = Reserved, forced by hardware to 0.

374/429

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