ST92F150CR1QB 查看數據表（PDF） - STMicroelectronics

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ST92F150CR1QB

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)

FUNCTIONAL DESCRIPTION (Cont’d)

3.2.3 Operation

The memory has a register interface mapped in

memory space (segment 22h). All operations are

enabled through the FCR (Flash Control Register),

ECR (E3 TM Control Register).

All operations on the Flash must be executed from

another memory (internal RAM, E3 TM, external

memory).

Flash (including TestFlash) and E3 TM are inde-

pendent, this means that one can be read while

the other is written. However simultaneous Flash

and E3 TM write operations are forbidden.

An interrupt can be generated at the end of a

Flash or an E3 TM write operation: this interrupt is

multiplexed with an external interrupt EXTINTx

(device dependent) to generate an interrupt INTx.

The status of a write operation inside the Flash

and the E3 TM memories can be monitored through

the FESR[1:0] registers.

Control and Status registers are mapped in mem-

ory (segment 22h), as shown in the following fig-

ure.

Figure 32. Control and Status Register Map.

Register Interface

224000h / 221000h

224001h / 221001h

224002h / 221002h

224003h / 221003h

FCR

ECR

FESR0

FESR1

In order to use the same data pointer register

(DPR) to point both to the E3 TM (220000h-

2203FFh) and to these control and status regis-

ters, the Flash and E3 TM control registers are

mapped not only at page 0x89 (224000h-

224003h) but also on page 0x88 (221000h-

221003h).

If the RESET pin is activated during a write opera-

tion, the write operation is interrupted. In this case

the user must repeat this last write operation fol-

lowing power on or reset. If the internal supply volt-

age drops below the VIT- threshold, a reset se-

quence is generated automatically by hardware.

3.2.4 E3 TM Update Operation

The update of the E3 TM content can be made by

pages of 16 consecutive bytes. The Page Update

operation allows up to 16 bytes to be loaded into

the RAM buffer that replace the ones already con-

tained in the specified address.

Each time a Page Update operation is executed in

the E3 TM, the RAM buffer content is programmed

in the next free block relative to the specified page

(the RAM buffer is previously automatically filled

with old data for all the page addresses not select-

ed for updating). If all the 4 blocks of the specified

page in the current E3 TM sector are full, the page

content is copied to the complementary sector,

that becomes the new current one.

After that the specified page has been copied to

the next free block, one erase phase is executed

on the complementary sector, if the 4 erase phas-

es have not yet been executed. When the selected

page is copied to the complementary sector, the

remaining 63 pages are also copied to the first

block of the new sector; then the first erase phase

is executed on the previous full sector. All this is

executed in a hidden manner, and the End Page

Update Interrupt is generated only after the end of

the complete operation.

At Reset the two status pages are read in order to

detect which is the sector that is currently mapping

the E3 TM, and in which block each page is

mapped. A system defined routine written in Test-

Flash is executed at reset, so that any previously

aborted write operation is restarted and complet-

ed.

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