LT3640IUFD 查看數據表（PDF） - Linear Technology

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LT3640IUFD

Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer

Linear Technology 

LT3640

Applications Information

Setting the Output Voltages

The internal reference voltage is 1.265V for the high volt-

age channel, and 600mV for the low voltage channel. The

output voltages are set by resistor dividers according to

the following formulas:

R2

=

R1 •





VOUT1

1.265V

−

1

R4

=

R3

•





VOUT2

0.6V

−

1

Use 1% resistors in the resistor dividers. To avoid noise

problems, R1 should be 100k or less, and R3 should

be 50k or less. Reference designators refer to the Block

Diagram.

Switching Frequency

The LT3640 uses a constant-frequency PWM architecture

that can be programmed to switch from 350kHz to 2.2MHz

by using a resistor tied from the RT pin to ground. Table

1 shows the necessary RT value for a desired switching

frequency.

Table 1. Switching Frequency vs RT Value

SWITCHING FREQUENCY (MHz)

0.35

0.5

1

2

2.2

RT (k)

267

182

82.5

32.4

27.4

Selection of the operating frequency is mainly a trade-off

between efficiency and component size. The advantage

of high frequency operation is that smaller inductor and

capacitor values may be used. The disadvantage is lower

efficiency.

The high switching frequency also decreases the duty

cycle range. The reason is that the LT3640 switches have

finite minimum on- and off-times independent of the

switching frequency. The top switch in the high voltage

channel can turn on for a minimum of ~60ns and turn off

for a minimum of ~70ns. The top switch in the low voltage

channel can turn on for a minimum of ~110ns and turn

12

off for a minimum of ~70ns. The minimum and maximum

duty cycles are:

DCMIN = fS • tON(MIN)

DCMAX = 1 – fS • tOFF(MIN)

where fS is the switching frequency, tON(MIN) is the mini-

mum switch on-time, and tOFF(MIN) is the minimum switch

off-time. These equations illustrate how duty cycle range

increases when switching frequency decreases.

The internal oscillator of the LT3640 can be synchronized

to an external 350kHz to 2.5MHz positive clock signal on

the SYNC pin. The RT value should be chosen such that

the internal oscillator’s frequency is 20% lower than the

lowest SYNC clock frequency (refer to Table 1). To avoid

erratic operation, the LT3640 ignores the SYNC signal

until the FB1 pin voltage is above 1.165V. When applying

a SYNC signal, the rising edges reset the LT3640’s internal

clock and initiate a switch cycle. The amplitude of the

SYNC signal must be at least 2V. The SYNC pulse width

must be at least 40ns.

VIN Voltage Range

The LT3640’s minimum operating voltage is 3.6V typical.

A higher minimum operating voltage can be accurately

programmed with a resistor divider between the VIN pin

and the EN/UVLO pin. The EN/UVLO threshold is 1.26V.

When the LT3640 is enabled, a 2µA current flows out of the

EN/UVLO pin generating hysteresis to prevent the switch-

ing action from falsely disabling the LT3640. Choose the

divider resistances for appropriate hysteresis voltage.

The high voltage nonsynchronous channel operates from

the VIN pin. The minimum VIN voltage to regulate output

voltage is:

VIN(MIN) =

 VOUT1 + VD 

 DCMAX 

− VD + VCE

Where VD is the forward voltage drop of the catch diode, VCE

is the voltage drop of the internal NPN power switch, and

DCMAX is the maximum duty cycle (refer to the Switching

Frequency section). If VIN is below the calculated minimum

voltage, output will lose regulation.

3640f

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