LTC1096AI(RevB) 查看數據表（PDF） - Linear Technology
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LTC1096AI Datasheet PDF : 28 Pages
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LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL APPLICATI S
Interfacing to the Parallel Port of the
Intel 8051 Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1098(L) and parallel port micro-
processors. Normally the CS, CLK and DIN signals would
be generated on three port lines and the DOUT signal read
on a fourth port line. This works very well. However, we
will demonstrate here an interface with the DIN and DOUT
of the LTC1098(L) tied together as described in the
SERIAL INTERFACE section. This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1098(L) over the data line connected to P1.2. Then
P1.2 is reconfigured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
LABEL
LOOP 1
LOOP
MNEMONIC
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
SETB
OPERAND
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
P1.3
R4, LOOP
R2, A
P1.4
COMMENTS
DIN word for LTC1098(L)
Make sure CS is high
CS goes low
Load counter
Rotate DIN bit into Carry
CLK goes low
Output DIN bit to LTC1098(L)
CLK goes high
Next bit
Bit 2 becomes an input
CLK goes low
Load counter
Read data bit into Carry
Rotate data bit into Acc.
CLK goes high
CLK goes low
Next bit
Store MSBs in R2
CS goes high
ANALOG
INPUTS
CS
LTC1098(L) CLK
DOUT
DIN
MUX ADDRESS
A/D RESULT
P1.4
P1.3
8051
P1.2
LTC1096/8 • TA06
DOUT from LTC1098(L) Stored in 8051 RAM
MSB
LSB
R2 B7 B6 B5 B4 B3 B2 B1 B0
LTC1096/8 • TA07
MSBF BIT LATCHED
CS
BY LTC1098(L)
1
2
3
4
CLK
DATA (DIN/DOUT)
START
SGL/
DIFF
ODD/ MSBF
SIGN
8051 P1.2 OUTPUTS DATA
TO LTC1098(L)
8051 P1.2 RECONFIGURED
AS AN INPUT AFTER THE 4TH RISING
CLK AND BEFORE THE 4TH FALLING CLK
B7
B6
B5
B4
B3
B2
B1
B0
LTC1098(L) SENDS A/D RESULT
BACK TO 8051 P1.2
LTC1098(L) TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
LTC1096/8 • TA08
24
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