LTC1402CGN 查看數據表（PDF） - Linear Technology

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LTC1402CGN

Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown

Linear Technology 

LTC1402

APPLICATIONS INFORMATION

0000 0000 0000 and 0000 0000 0001. For full-scale ad-

justment in Figures 10a and 10b, apply an input voltage of

2.0465V (FS – 1.5LSBs) to AIN+ and adjust R5 until the

output code flickers between 1111 1111 1110 and 1111

1111 1111.

BOARD LAYOUT AND BYPASSING

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1402, a printed circuit board

with ground plane is required. Layout for the printed

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track.

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 2 (AGND1), Pin 6 (AGND2), Pin 13 (DGND) and all

other analog grounds should be connected directly to an

analog ground plane. Pin 9 (OGND) should be connected

near Pin13 (DGND), where the analog ground plane ties to

the logic system ground. The VREF bypass capacitor and

the DVDD bypass capacitor should also be connected to

this analog ground plane, see Figure 11. No other digital

grounds should be connected to this analog ground plane.

Low impedance analog and digital power supply common

returns are essential to low noise operation of the ADC and

the foil width for these tracks should be as wide as

possible. The traces connecting the pins and bypass

capacitors must be kept short and should be made as wide

as possible.

The LTC1402 has differential inputs to minimize noise

coupling. Common mode noise on the AIN+ and AIN– leads

will be rejected by the input CMRR. The AIN– input can be

used as a ground sense for the AIN+ input; the LTC1402 will

hold and convert the difference voltage between AIN+ and

AIN– . The leads to AIN+ (Pin 3) and AIN– (Pin 4) should be

kept as short as possible. In applications where this is not

possible, the AIN+ and AIN– traces should be run side-by-

side to cancel noise coupling.

SUPPLY BYPASSING

High quality, low series resistance 10µF ceramic bypass

capacitors should be used at the VDD and VREF pins.

Surface mount ceramic capacitors such as Murata

GRM235Y5V106Z016 provide excellent bypassing in a

small board space. Alternatively, 10µF tantalum capaci-

tors in parallel with 0.1µF ceramic capacitors can be used.

Bypass capacitors must be located as close to the pins as

possible. The traces connecting the pins and the bypass

capacitors must be kept short and should be made as wide

as possible.

POWER-DOWN MODES

Upon power-up, the LTC1402 is initialized to the active

state and is ready for conversion. The Nap and Sleep Mode

waveforms show the power-down modes for the LTC1402.

The SCK and CONV inputs control the power-down modes

(see Timing Diagrams). Two rising edges at CONV, with-

out any intervening rising edges at SCK, put the LTC1402

in Nap mode and the power drain drops from 90mW to

3 AIN+

ANALOG

INPUT

CIRCUITRY

+–

AIN– VREF

4

5

AGND2

6

10µF

LTC1402

VSS

14

AGND1

2

10µF

AVDD DVDD DGND

1 12 13

10µF

12

OVDD

DOUT 10

OGND

9

3V TO 5V

DIGITAL

SYSTEM

SYSTEM

GROUND

1402 F11

ANALOG GROUND PLANE

Figure 11. Power Supply Grounding Practice

15

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