LTC1821BCGW 查看數據表（PDF） - Linear Technology

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LTC1821BCGW

16-Bit, Ultra Precise, Fast Settling VOUT DAC

Linear Technology 

LTC1821

TRUTH TABLE

Table 1

CONTROL INPUTS

CLR WR LD

0XX

100

111

101

1

110

REGISTER OPERATION

Reset Input and DAC Register to All 0s for LTC1821 and Midscale for LTC1821-1 (Asynchronous Operation)

Write Input Register with All 16 Data Bits

Load DAC Register with the Contents of the Input Register

Input and DAC Register Are Transparent

CLK = LD and WR Tied Together. The 16 Data Bits Are Written Into the Input Register on the Falling Edge of the CLK and Then

Loaded Into the DAC Register on the Rising Edge of the CLK

No Register Operation

BLOCK DIAGRA

REF 8

12k

48k

48k

48k

RCOM 9

12k

R1 10

48k

48k

48k

48k

48k

48k

96k

96k

12k

96k 96k 12k

–

VCC 2

+

DECODER

LD 23

D15

D14

LOAD (MSB)

D13

D12

DAC REGISTER

D11 • • •

D0

(LSB) RST

WR 24

WR

25 26

D15 D14

INPUT REGISTER

RST

••••

*CONNECTED INTERNALLY.

36

3

4

5

6

DO NOT CONNECT EXTERNAL

D4 D3 D2 D1 D0

CIRCUITRY TO THESE PINS

12 RFB

11 ROFS

14 IOUT

15 V+

13 VOUT

20 V–

16 AGNDS

17 AGNDF

7 CLR

18 DNC*

19 DNC*

21 DNC*

22 NC

1 DGND

1821 BD

8

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