LTC2264-14(RevB) 查看數據表（PDF） - Linear Technology

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LTC2264-14
(Rev.:RevB)

14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs

Linear Technology 

LTC2265-14/

LTC2264-14/LTC2263-14

PIN FUNCTIONS

AIN1+ (Pin 1): Channel 1 Positive Differential Analog

Input.

AIN1– (Pin 2): Channel 1 Negative Differential Analog

Input.

VCM1 (Pin 3): Common Mode Bias Output, Nominally Equal

to VDD/2. VCM should be used to bias the common mode

of the analog inputs of channel 1. Bypass to ground with

a 0.1µF ceramic capacitor.

REFH (Pins 4, 5): ADC High Reference. Bypass to pins 6, 7

with a 2.2µF ceramic capacitor, and to ground with a 0.1µF

ceramic capacitor.

REFL (Pins 6, 7): ADC Low Reference. Bypass to pins 4, 5

with a 2.2µF ceramic capacitor, and to ground with a 0.1µF

ceramic capacitor.

VCM2 (Pin 8): Common Mode Bias Output, Nominally Equal

to VDD/2. VCM should be used to bias the common mode

of the analog inputs of channel 2. Bypass to ground with

a 0.1µF ceramic capacitor.

AIN2+ (Pin 9): Channel 2 Positive Differential Analog

Input.

AIN2– (Pin 10): Channel 2 Negative Differential Analog

Input.

VDD (Pins 11, 12, 39, 40): 1.8V Analog Power Supply.

Bypass to ground with 0.1µF ceramic capacitors. Adjacent

pins can share a bypass capacitor.

ENC+ (Pin 13): Encode Input. Conversion starts on the

rising edge.

ENC– (Pin 14): Encode Complement Input. Conversion

starts on the falling edge.

CS (Pin 15): In serial programming mode (PAR/SER = 0V),

CS is the serial interface chip select input. When CS is low,

SCK is enabled for shifting data on SDI into the mode

control registers. In parallel programming mode (PAR/SER

= VDD), CS selects 2-lane or 1-lane output mode. CS can

be driven with 1.8V to 3.3V logic.

SCK (Pin 16): In serial programming mode (PAR/SER

= 0V), SCK is the serial interface clock input. In parallel

programming mode (PAR/SER = VDD), SCK selects 3.5mA

or 1.75mA LVDS output currents. SCK can be driven with

1.8V to 3.3V logic.

SDI (Pin 17): In serial programming mode (PAR/SER =

0V), SDI is the serial interface data input. Data on SDI

is clocked into the mode control registers on the rising

edge of SCK. In parallel programming mode (PAR/SER =

VDD), SDI can be used to power down the part. SDI can

be driven with 1.8V to 3.3V logic.

GND (Pins 18, 33, 37, Exposed Pad Pin 41): ADC Power

Ground. The exposed pad must be soldered to the PCB

ground.

OGND (Pin 25): Output Driver Ground. Must be shorted

to the ground plane by a very low inductance path. Use

multiple vias close to the pin.

OVDD (Pin 26): Output Driver Supply. Bypass to ground

with a 0.1µF ceramic capacitor.

SDO (Pin 34): In serial programming mode (PAR/SER

= 0V), SDO is the optional serial interface data output.

Data on SDO is read back from the mode control registers

and can be latched on the falling edge of SCK. SDO is an

open-drain NMOS output that requires an external 2k pull-

up resistor of 1.8V to 3.3V. If readback from the mode

control registers is not needed, the pull-up resistor is not

necessary and SDO can be left unconnected. In parallel

programming mode (PAR/SER = VDD), SDO is an input that

enables internal 100Ω termination resistors on the digital

outputs. When used as an input, SDO can be driven with

1.8V to 3.3V logic through a 1k series resistor.

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