LTC3717-1 查看數據表（PDF） - Linear Technology

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LTC3717-1

Wide Operating Range, No RSENSE™ Step-Down Controller for DDR/QDR Memory Termination

Linear Technology 

LTC3717-1

APPLICATIO S I FOR ATIO

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

• Place CIN, COUT, MOSFETs, D1 and inductor all in one

compact area. It may help to have some components on

the bottom side of the board.

• Place LTC3717-1 chip with Pins 15 to 28 facing the

power components. Keep the components connected

to Pins 1 to 10 close to LTC3717-1 (noise sensitive

components).

• Use an immediate via to connect the components to

ground plane including SGND and PGND of LTC3717-1.

Use several bigger vias for power components.

• Use compact plane for switch node (SW) to improve

cooling of the MOSFETs and to keep EMI down.

• Use planes for VIN and VOUT to maintain good voltage

filtering and to keep power losses low.

• Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of

power component. You can connect the copper areas to

any DC net (VIN, VOUT, GND or to any other DC rail in

your system).

When laying out a printed circuit board, without a ground

plane, use the following checklist to ensure proper opera-

tion of the controller. These items are also illustrated in

Figure 8.

• Segregate the signal and power grounds. All small

signal components should return to the SGND pin at

one point which is then tied to the PGND pin close to the

source of M2.

• Place M2 as close to the controller as possible, keeping

the PGND, BG and SW traces short.

• Connect the input capacitor(s) CIN close to the power

MOSFETs. This capacitor carries the MOSFET AC cur-

rent.

• Keep the high dV/dT SW, BOOST and TG nodes away

from sensitive small-signal nodes.

• Connect the INTVCC and DRVCC decoupling capacitor

CVCC closely to the INTVCC, DRVCC and PGND pins.

• Connect the top driver boost capacitor CB closely to the

BOOST and SW pins.

• Connect the VCC pin decoupling capacitor CF closely to

the VCC and PGND pins.

CSS

CC1 RC

CION

CFB

RUN/SS BOOST

PGOOD

TG

LTC3717-1

VRNG

SW

SENSE+

ITH

PGND

CC2

SENSE–

SGND

BG

VON

ION

INTVCC

DRVCC

VFB

VCC

VREF

RON

EXTVCC

CB

L

DB

CVCC

M1

D2

M2

D1

CIN

CF

RF

COUT

+

VIN

–

–

VOUT

+

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 8. LTC3717-1 Layout Diagram

37171 F08

sn37171 37171fs

17

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