LTM2883 查看數據表（PDF） - Linear Technology

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LTM2883

SPI/Digital or I2C µModule Isolator with Adjustable ±12.5V and 5V Regulated Power

Linear Technology 

LTM2883

Applications Information

Table 4. Unidirectional SPI Timing Event Description

TIME

CPHA EVENT DESCRIPTION

t0

t0 to t1

0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns

0, 1 Propagation delay chip select, logic to isolated side

t2

0

Start of data transmission, data set-up

1

Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

t2 to t3

0

Propagation delay of data, logic side to isolated side

1

Propagation delay of data and clock, logic side to isolated side

t3

t3 to t5

0, 1 Logic side data sample time, half clock period delay from data set-up transition

0, 1 Clock propagation delay, clock and data transition

t4 to t5

0, 1 Data to clock delay, must be ≤13ns

t5 to t6

t5 to t7

t8

0, 1 Clock to data delay, must be ≤3ns

0, 1 Data and clock propagation delay

0

Last clock and data transition

1

Last clock transition

t8 to t9

0

Clock and data propagation delay

1

Clock propagation delay

t9 to t10

t11

t12

1

Data propagation delay

0, 1 Asynchronous chip select transition, end of transmission

0, 1 Chip select transition isolated side

rate is 400kHz which supports fast-mode I2C. Timing is

detailed in Figure 10. The data rate is limited by the slave

acknowledge setup time (tSU;ACK), consisting of the I2C

standard minimum setup time (tSU;DAT) of 100ns, maximum

clock propagation delay of 225ns, glitch filter and isolated

data delay of 350ns maximum, and the combined isolated

and logic data fall time of 500ns at maximum bus load-

ing. The total setup time reduces the I2C data hold time

(tHD;DAT) to a maximum of 125ns, guaranteeing sufficient

data setup time (tSU;ACK).

The isolated side bidirectional serial data pin, SDA2,

simplified schematic is shown in Figure 11. An internal

1.8mA current source provides a pull-up for SDA2. Do not

connect any other pull-up device to SDA2. This current

source is sufficient to satisfy the system requirements for

bus capacitances greater than 200pF in FAST mode and

greater than 400pF in STANDARD mode.

Additional proprietary circuitry monitors the slew rate on

the SDA and SDA2 signals to manage directional control

across the isolation barrier. Slew rates on both pins must

be greater than 1V/μs for proper operation.

The logic side bidirectional serial data pin, SDA, requires a

pull-up resistor or current source connected to VL. Follow

SDA

SDA2

SCL

SCL2

SLAVE ACK

1

8

9

START

tPROP

tSU;DAT

tHD;DAT

Figure 10. I2C Timing Diagram

tSU;ACK

STOP 2883 F10

2883f

21

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