M24C02-RMN6TP 查看數據表（PDF） - STMicroelectronics
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M24C02-RMN6TP Datasheet PDF : 39 Pages
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M24C16, M24C08, M24C04, M24C02, M24C01
DC and AC parameters
Table 15. AC characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R,
M24Cxx-F)
Test conditions specified in either Table 6, Table 7 or Table 8 and Table 13
Symbol Alt.
Parameter
Min.(1) Max.(1) Unit
fC
fSCL Clock frequency
tCHCL
tHIGH Clock pulse width high
tCLCH
tQL1QL2(2)
tLOW
tF
Clock pulse width low
SDA (out) fall time
tXH1XH2
tR Input signal rise time
tXL1XL2
tF Input signal fall time
tDXCX tSU:DAT Data in set up time
tCLDX tHD:DAT Data in hold time
tCLQX
tDH Data out hold time
tCLQV(5)(6) tAA Clock low to next data valid (access time)
tCHDL tSU:STA Start condition setup time
tDLCL tHD:STA Start condition hold time
tCHDH tSU:STO Stop condition set up time
tDHDL
tBUF
Time between Stop condition and next Start
condition
400
kHz
600
ns
1300
ns
20(3)
120
ns
(4)
(4)
ns
(4)
(4)
ns
100
ns
0
ns
100
ns
200
900
ns
600
ns
600
ns
600
ns
1300
ns
tW
tWR Write time
5
ms
1. All values are referred to VIL(max) and VIH(min).
2. Characterized only, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5.
Doc ID 5067 Rev 16
23/39
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