M25PE80-VMN6TP 查看數據表（PDF） - STMicroelectronics

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M25PE80-VMN6TP

8 Mbit, low-voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

Instructions

M25PE80

6.8

Read Lock Register (RDLR)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Lock Register (RDLR) instruction is followed by a 3-Byte address (A23-A0) pointing to any

location inside the concerned sector (or subsector). Each address bit is latched-in during

the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on

Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the

falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 14.

The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at

any time during data output.

Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Table 10. Lock Registers

Bit

Bit Name Value

Function

b7-b4

Reserved

The Write Lock and Lock Down Bits cannot be changed. Once a

‘1’ ‘1’ is written to the Lock Down Bit it cannot be cleared to ‘0’,

b1

Sector Lock

Down

except by a Reset or power-up.

‘0’

The Write Lock and Lock Down Bits can be changed by writing

new values to them. (Default value).

b0

Sector Write

Lock

‘1’

Write, Program and Erase operations in this sector will not be

executed. The memory contents will not be changed.

‘0’

Write, Program and Erase operations in this sector are executed

and will modify the sector contents. (Default value).

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