M50FLW040AN5TP 查看數據表（PDF） - STMicroelectronics

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M50FLW040AN5TP

4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

STMicroelectronics 

M50FLW040A, M50FLW040B

Bus operations

Table 9. LPC bus write field definitions (1 byte)

Clock Clock

Cycle Cycle

Number Count

Field

LAD0- Memory

LAD3

I/O

Description

On the rising edge of CLK with LFRAME Low,

1

1

START 0000b

I the contents of LAD0-LAD3 must be 0000b to

indicate the start of a LPC cycle.

2

1

CYCTYPE

+ DIR

011Xb

Indicates the type of cycle. Bits 3:2 must be 01b.

I Bit 1 indicates the direction of transfer: 1b for

write. Bit 0 is don’t care (X).

3-10

8

ADDR XXXX

11-12 2

DATA

XXXX

A 32-bit address is transferred, with the most

significant nibble first. A23-A31 must be set to 1.

I A22=1 for memory access, and A22=0 for

register access. Table 5 shows the appropriate

values for A21-A19.

I

Data transfer is two cycles, starting with the

least significant nibble.

13

1

TAR

1111b

I

The host drives LAD0-LAD3 to 1111b to indicate

a turnaround cycle.

14

1

TAR

1111b

(float)

O

The LPC Flash Memory takes control of LAD0-

LAD3 during this cycle.

The LPC Flash Memory drives LAD0-LAD3 to

15

1

SYNC 0000b

O 0000b, indicating it has received data or a

command.

16

1

TAR

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to

1111b, indicating a turnaround cycle.

17

1

TAR

1111b

(float)

N/A

The LPC Flash Memory floats its outputs and

the host takes control of LAD0-LAD3.

Figure 9. LPC bus write waveforms (1 byte)

CLK

LFRAME

LAD0-LAD3

Number of

clock cycles

START

1

CYCTYPE

+ DIR

1

ADDR

8

DATA

2

Table 10. A/A Mux bus operations

Operation

G

W

RP

Bus Read

Bus Write

Output Disable

Reset

VIL

VIH

VIH

VIH

VIL

VIH

VIH

VIH

VIH

VIL or VIH VIL or VIH

VIL

TAR

2

SYNC

1

VPP

Don't Care

VCC or VPPH

Don't Care

Don't Care

TAR

2

AI04430

DQ7-DQ0

Data Output

Data Input

Hi-Z

Hi-Z

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