MB90660A Series
Mnemonic
ANDL A, ear
ANDL A, eam
ORL A, ear
ORL A, eam
XORL A, ea
XORL A, eam
Table 14 Logical 2 Instructions (Long Word) [6 Instructions]
# ~ RG B
Operation
LH AH I S T N Z V C RMW
2 6 2 0 long (A) ← (A) and (ear) – – – – – * * R – –
2+ 7+ (a) 0 (d) long (A) ← (A) and (eam) – – – – – * * R – –
2 6 2 0 long (A) ← (A) or (ear)
2+ 7+ (a) 0 (d) long (A) ← (A) or (eam)
––––– * *R– –
––––– * *R– –
2 6 2 0 long (A) ← (A) xor (ear) – – – – – * * R – –
2+ 7+ (a) 0 (d) long (A) ← (A) xor (eam) – – – – – * * R – –
Mnemonic
NEG A
NEG ear
NEG eam
NEGW A
NEGW ear
NEGW eam
Table 15 Sign Inversion Instructions (Byte/Word) [6 Instructions]
# ~ RG B
Operation
1 2 0 0 byte (A) ← 0 – (A)
LH AH I S T N Z V C RMW
X–––– * * * * –
2 3 2 0 byte (ear) ← 0 – (ear)
–––––* * * * –
2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam) – – – – – * * * * *
1 2 0 0 word (A) ← 0 – (A)
–––––* * * * –
2 3 2 0 word (ear) ← 0 – (ear) – – – – – * * * * –
2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam) – – – – – * * * * *
Table 16 Normalize Instruction (Long Word) [1 Instruction]
Mnemonic
NRML A, R0
# ~ RG B
Operation
LH AH I S T N Z V C RMW
2 *1 1
0 long (A) ← Shift until first digit is “1” – – – – – – * – – –
byte (R0) ← Current shift count
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
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