S9S08QD4CSC 查看數據表（PDF） - Freescale Semiconductor
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S9S08QD4CSC Datasheet PDF : 198 Pages
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9.3.3 ICS Trim Register (ICSTRM)
Internal Clock Source (S08ICSV1)
7
R
W
POR:
1
Reset:
U
6
5
4
3
TRIM
2
1
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
Figure 9-5. ICS Trim Register (ICSTRM)
Table 9-3. ICS Trim Register Field Descriptions
Field
7:0
TRIM
Description
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
9.3.4 ICS Status and Control (ICSSC)
7
R
0
W
POR:
0
Reset:
0
6
5
4
0
0
0
0
0
0
0
0
0
3
2
CLKST
0
0
0
0
1
OSCINIT
0
FTRIM
0
0
0
U
Figure 9-6. ICS Status and Control Register (ICSSC)
Table 9-4. ICS Status and Control Register Field Descriptions
Field
7:4
3:2
CLKST
1
0
Description
Reserved, must be cleared.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Output of FLL is selected.
01 FLL Bypassed, Internal reference clock is selected.
10 FLL Bypassed, External reference clock is selected.
11 Reserved.
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is cleared only when either ERCLKEN or EREFS are cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Freescale Semiconductor
127
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