M48T08-100PC 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M48T08-100PC

CMOS 8K x 8 TIMEKEEPER SRAM

STMicroelectronics 

Figure 3. Block Diagram

M48Z02, M48Z12

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

POWER

VPFD

2K x 8

SRAM ARRAY

A0-A10

DQ0-DQ7

E

W

G

VCC

VSS

AI01255

READ MODE

The M48Z02,12 is in the Read Mode whenever W

(Write Enable) is high and E (Chip Enable) is low.

The device architecture allows ripple-through ac-

cess of data from eight of 16,384 locations in the

static storage array. Thus, the unique address

specified by the 11 Address Inputs defines which

one of the 2,048 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

within tAVQV (Address Access Time) after the last

address input signal is stable, providing that the E

and G access times are also satisfied. If the E and

G access times are not met, valid data will be

available after the latter of the Chip Enable Access

Time (tELQV) or Output Enable Access Time (tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activated

before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the AddressInputs

are changed while E and G remain active, output

data will remain valid for tAXQX (Output Data Hold

Time) but will go indeterminate until the next Ad-

dress Access.

AC MEASUREMENT CONDITIONS

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

≤ 5ns

0.6V to 2.4V

0.8V to 2.2V

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Figure 4. AC Testing Load Circuit

5V

DEVICE

UNDER

TEST

1kΩ

1.8kΩ

OUT

CL = 100pF

CL includes JIG capacitance

AI01019

3/12

Share Link: