MT90866 查看數據表（PDF） - Zarlink Semiconductor Inc
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MT90866
Zarlink Semiconductor Inc
MT90866 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
Read/Write Address: 002DH for DPOA Register
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POS POS POS POS POS POS POS
0
0
0
0
0
0
SKC2 SKC1 SKC0
6
5
4
3
2
1
0
Bit
15 - 9
8-3
2-0
Name
Description
POS6 - POS0
Unused
SKC2 - SKC0
Phase Offset Bits: These seven bits refer to the 2’s complement phase word to
control the DPLL output phase offset. The offset varies in steps of 15 ns if the
reference is 8 kHz or 2.048 MHz. The offset varies in steps of 20 ns if the reference
is 1.544 MHz.
Reserved.
Skew Control Bits: These three bits control the delay of the DPLL outputs from 0
to 7 steps in interval of maximum unit delay of 3.5 ns.
Table 23 - DPLL Output Adjustment (DPOA) Register Bits
Read/Write Address: 002EH for DHKR Register
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SLS PLS CKM
Limit
State 2 State 1 State 0
Bit
15 - 7
6
5
4
3
Name
Unused
SLS
PLS
CKM
Limit
Description
Reserved.
Secondary Loss Detection Bit (Read-only bit): This bit is the same as the output
from the DPLL Reference Monitor FAIL_SEC.
Primary Loss Detection Bit (Read-only bit): This bit is the same as the output from
the DPLL Reference Monitor FAIL_PRI.
DPLL Clock Monitor Bit: When high, the primary output C32/64o is 65.536 MHz clock.
When low, the primary output C32/64o is 32.768 MHz clock. This is the only writable bit
in this register.
Limit (Read-only bit): Indicates that DPLL Phase Slope limiter limits input phase.
Table 24 - DPLL House Keeping (DHKR) Register Bits
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