SAF-C505C-2RM 查看數據表（PDF） - Infineon Technologies
零件编号
产品描述 (功能)
生产厂家
SAF-C505C-2RM Datasheet PDF : 88 Pages
| |||
C505 / C505C
C505A / C505CA
8-Bit A/D Converter (C505 and C505C only)
The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog
input channels. It operates with a successive approximation technique and provides the following
features:
– 8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs
– 8-bit resolution
– Internal start-of-conversion trigger
– Interrupt request generation after each conversion
– Single or continuous conversion mode
The 8-bit ADC uses two clock signals for operation : the conversion clock fADC (=1/tADC) and the
input clock fIN (1/tIN). fADC is derived from the C505 system clock fOSC which is applied at the XTAL
pins via the ADC clock prescaler as shown in figure 17. The input clock is equal to fOSC. The
conversion clock fADC is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock
prescaler must be programmed to a value which assures that the conversion clock does not exceed
1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.
ADCL1
ADCL0
f OSC
32
16 MUX
8
4
Conversion Clock f ADC
A/D
Converter
Clock Prescaler
Input Clock f IN
Condition: f ADC max < 1.25 MHz
f IN = f OSC
=
1
CLP
MCU System Clock fIN
Rate (fOSC)
[MHz]
2 MHz
2
5 MHz
5
6 MHz
6
10 MHz
10
12 MHz
12
16 MHz
16
20 MHz
20
Prescaler
Ratio
÷4
÷4
÷8
÷8
÷ 16
÷ 16
÷ 16
fADC
[MHz]
0.5
1.25
0.75
1.25
0.75
1
1.25
Figure 17
8-Bit A/D Converter Clock Selection
Data Sheet
38
MCS03299
ADCL1 ADCL0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
08.00
Share Link: 