PCA85176(2010) 查看數據表（PDF） - NXP Semiconductors.
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PCA85176 Datasheet PDF : 44 Pages
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NXP Semiconductors
PCA85176
Universal LCD driver for low multiplex rates
data output
by transmitter
data output
by receiver
SCL from
master
S
1
2
START
condition
Fig 15. Acknowledgement of the I2C-bus
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
mbc602
7.16.5 I2C-bus controller
The PCA85176 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCA85176 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
7.16.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCA85176. The entire I2C-bus slave address byte is shown in Table 7.
Table 7. I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
0
1
1
1
0
0
SA0
R/W
The PCA85176 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte that a PCA85176 will respond to,
is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Having two reserved slave addresses allows the following on the same I2C-bus:
PCA85176_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 14 April 2010
© NXP B.V. 2010. All rights reserved.
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