ST72521R7TC 查看數據表（PDF） - STMicroelectronics

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ST72521R7TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

CONTROLLER AREA NETWORK (Cont’d)

10.8.4 Register Description

The CAN registers are organized as 6 general pur-

pose registers plus 5 pages of 16 registers span-

ning the same address space and primarily used

for message and filter storage. The page actually

selected is defined by the content of the Page Se-

lection Register. Refer to Figure 72.

10.8.4.1 General Purpose Registers

INTERRUPT STATUS REGISTER (ISR)

Read/Write

Reset Value: 00h

7

0

RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND

−BitR7e=adR/CXIleFa3rReceive Interrupt Flag for Buffer 3

Set by hardware to signal that a new error-free mes-

sage is available in buffer 3.

Cleared by software to release buffer 3.

Also cleared by resetting bit RDY of BCSR3.

−BitR6e=adR/CXIleFa2rReceive Interrupt Flag for Buffer 2

Set by hardware to signal that a new error-free

message is available in buffer 2.

Cleared by software to release buffer 2.

Also cleared by resetting bit RDY of BCSR2.

B−itR5e=adR/CXIleFa1rReceive Interrupt Flag for Buffer 1

Set by hardware to signal that a new error-free mes-

sage is available in buffer 1.

Cleared by software to release buffer 1.

Also cleared by resetting bit RDY of BCSR1.

B−itR4e=adT/XCIlFeaTrransmit Interrupt Flag

Set by hardware to signal that the highest priority

message queued for transmission has been suc-

cessfully transmitted (ETX = 0) or that it has passed

successfully the arbitration (ETX = 1).

Cleared by software.

B−itR3e=adS/CCIlFeaSr tatus Change Interrupt Flag

Set by hardware to signal the reception of a domi-

nant bit while in standby or a change from error ac-

tive to error passive and bus-off while in run. Also

signals any receive error when ESCI = 1.

Cleared by software.

B−itR2e=adO/CRlIeFaOr verrun Interrupt Flag

Set by hardware to signal that a message could not

be stored because no receive buffer was available.

Cleared by software.

Bit 1 = TEIF Transmit Error Interrupt Flag

− Read/Clear

Set by hardware to signal that an error occurred dur-

ing the transmission of the highest priority message

queued for transmission.

Cleared by software.

B−itR0e=adEPONnDly Error Interrupt Pending

Set by hardware when at least one of the three error

interrupt flags SCIF, ORIF or TEIF is set.

Reset by hardware when all error interrupt flags

have been cleared.

Caution;

Interrupt flags are reset by writing a "0" to the cor-

responding bit position. The appropriate way con-

sists in writing an immediate mask or the one’s com-

plement of the register content initially read by the

interrupt handler. Bit manipulation instruction

BRES should never be used due to its read-modify-

write nature.

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