ST7LITES2 查看數據表（PDF） - STMicroelectronics
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ST7LITES2
STMicroelectronics
ST7LITES2 Datasheet PDF : 125 Pages
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ST7LITE0x, ST7LITESx
OPTION BYTES (Cont’d)
OPTION BYTE 1
Bit 7 = PLLx4x8 PLL Factor selection.
0: PLLx4
1: PLLx8
Bit 6 = PLLOFF PLL disabled
0: PLL enabled
1: PLL disabled (by-passed)
Bit 4 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
Note: If the RC oscillator is selected, then to im-
prove clock stability and frequency accuracy, it is
recommended to place a decoupling capacitor,
typically 100nF, between the VDD and VSS pins as
close as possible to the ST7 device.
Bit 5 = Reserved, must always be 1.
Table 21. List of valid option combinations
Operating conditions
VDD range
Clock Source
PLL
Typ fCPU
off
0.7MHz @3V
Internal RC 1%
x4
2.8MHz @3V
2.4V - 3.3V
x8
-
off
0-4MHz
External clock
x4
4MHz
x8
-
off
1MHz @5V
Internal RC 1%
x4
-
3.3V - 5.5V
x8
8MHz @5V
off
0-8MHz
External clock
x4
-
x8
8 MHz
Note: see Clock Management Block diagram in Figure 13
OSC
0
0
-
1
1
-
0
-
0
1
-
1
Option Bits
PLLOFF
1
0
-
1
0
-
1
-
0
1
-
0
PLLx4x8
1
0
-
1
0
-
1
-
1
1
-
1
Bits 3:2 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se-
lected threshold as shown in Table 22.
Table 22. LVD Threshold Configuration
Configuration
LVD1 LVD0
LVD Off
11
Highest Voltage Threshold (∼4.1V)
10
Medium Voltage Threshold (∼3.5V)
01
Lowest Voltage Threshold (∼2.8V)
00
Bit 1 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Bit 0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
7
Default
Value
1
OPTION BYTE 0
07
Reserved
SEC1 SEC0
FMP
R
FMP
W
PLL
x4x8
PLL
OFF
111110011
OPTION BYTE 1
0
OSC
LVD1
LVD0
WDG
SW
WDG
HALT
101111
115/125
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