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ST7LITES2 查看數據表(PDF) - STMicroelectronics

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ST7LITES2 Datasheet PDF : 125 Pages
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ST7LITE0x, ST7LITESx
11.3 SERIAL PERIPHERAL INTERFACE (SPI)
11.3.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
11.3.2 Main Features
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (fCPU/4 max.)
fCPU/2 max. slave mode frequency (see note)
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
11.3.3 General Description
Figure 36 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
Figure 36. Serial Peripheral Interface Block Diagram
Data/Address Bus
SPIDR
Read
Read Buffer
Interrupt
request
MOSI
MISO
SOD
bit
SCK
8-Bit Shift Register
Write
7
SPIF WCOL OVR MODF 0
SPICSR 0
SOD SSM SSI
SPI
STATE
CONTROL
SS 1
0
MASTER
CONTROL
7
SPICR 0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
SERIAL CLOCK
GENERATOR
SS
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