10F200 查看數據表（PDF） - Microchip Technology
零件编号
产品描述 (功能)
生产厂家
10F200 Datasheet PDF : 96 Pages
| |||
PIC10F200/202/204/206
12.3 DC Characteristics: PIC10F200/202/204/206 (Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating voltage VDD range as described in DC specification
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
VIL Input Low Voltage
I/O ports:
D030
with TTL buffer
Vss
—
0.8
V For all 4.5 ≤ VDD ≤ 5.5V
D030A
Vss
— 0.15 VDD V Otherwise
D031
with Schmitt Trigger
buffer
Vss
— 0.2 VDD V
D032
MCLR, T0CKI
Vss
— 0.2 VDD V
VIH Input High Voltage
I/O ports:
—
D040
with TTL buffer
2.0
—
VDD
V 4.5 ≤ VDD ≤ 5.5V
D040A
0.25 VDD + 0.8 —
VDD
V Otherwise
D041
with Schmitt Trigger
buffer
0.8VDD
—
VDD
V For entire VDD range
D042
D070
IPUR
IIL
MCLR, T0CKI
GPIO weak pull-up current(3)
Input Leakage Current(1, 2)
0.8VDD
50
—
VDD
250 400
V
μA VDD = 5V, VPIN = VSS
D060
D061
I/O ports
GP3/MCLR(4)
—
±0.1 ± 1
μA Vss ≤ VPIN ≤ VDD, Pin at high-imped-
ance
—
±0.7 ± 5
μA Vss ≤ VPIN ≤ VDD
Output Low Voltage
D080
I/O ports
—
—
0.6
V IOL = 8.5 mA, VDD = 4.5V, -40°C to
+85°C
D080A
—
—
0.6
V IOL = 7.0 mA, VDD = 4.5V, -40°C to
+125°C
D090
Output High Voltage
I/O ports(2)
VDD – 0.7
—
—
V IOH = -3.0 mA, VDD = 4.5V, -40°C to
+85°C
D090A
VDD – 0.7
—
—
V IOH = -2.5 mA, VDD = 4.5V, -40°C to
+125°C
Capacitive Loading Specs on Output Pins
D101
All I/O pins
—
—
50*
pF
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
* These parameters are for design guidance only and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as coming out of the pin.
3: This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the
MCLR circuit is higher than the standard I/O logic.
© 2007 Microchip Technology Inc.
DS41239D-page 67
Share Link: 