PIC10F220/222
8.8 Reset on Brown-out
A Brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
Brown-out.
To reset PIC10F220/222 devices when a Brown-out
occurs, external Brown-out protection circuits may be
built, as shown in Figure 8-7 and Figure 8-8.
FIGURE 8-7:
VDD
33k
10k
BROWN-OUT
PROTECTION CIRCUIT 1
VDD
Q1 MCLR(2) PIC10F22X
40k(1)
Note 1:
2:
This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
Pin must be configured as MCLR.
FIGURE 8-8:
VDD
R1
R2
BROWN-OUT
PROTECTION CIRCUIT 2
VDD
Q1 MCLR(2) PIC10F22X
40k(1)
Note 1:
2:
This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
VDD •
R1
= 0.7V
R1 + R2
Pin must be configured as MCLR.
FIGURE 8-9:
BROWN-OUT
PROTECTION CIRCUIT 3
VDD
MCP809 Bypass
VSS
Capacitor
VDD
RST
VDD
MCLR(2)
PIC10F22X
Note 1:
This Brown-out Protection circuit employs
Microchip Technology’s MCP809 micro-
controller supervisor. There are 7 different
trip point selections to accommodate 5V to
3V systems.
2: Pin must be configured as MCLR.
8.9 Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
8.9.1 SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
Note: A Reset generated by a WDT time-out
does not drive the MCLR pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the GP3/
MCLR/VPP pin must be at a logic high level if MCLR is
enabled.
DS41270B-page 40
Preliminary
© 2006 Microchip Technology Inc.