PIC16LC73B-20E/SO 查看數據表（PDF） - Microchip Technology

零件编号

产品描述 (功能)

生产厂家

PIC16LC73B-20E/SO

8-Bit CMOS Microcontrollers with A/D Converter

Microchip Technology 

PIC16C63A/65B/73B/74B

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is TRISB. Setting a bit

in the TRISB register puts the corresponding output

driver in a hi-impedance input mode. Clearing a bit in

the TRISB register puts the contents of the output latch

on the selected pin(s).

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (OPTION_REG<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are dis-

abled on a Power-on Reset.

FIGURE 5-3:

RBPU(2)

Data Bus

WR Port

WR TRIS

BLOCK DIAGRAM OF

RB3:RB0 PINS

Data Latch

DQ

CK

VDD

P

Weak

Pull-up

I/O pin(1)

TRIS Latch

DQ

CK

TTL

Input

Buffer

RD TRIS

RD Port

QD

EN

RB0/INT

Schmitt Trigger

Buffer

RD Port

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (OPTION_REG<7>).

Four of PORTB’s pins, RB7:RB4, have an

interrupt-on-change feature. Only pins configured as

inputs can cause this interrupt to occur (i.e., any

RB7:RB4 pin configured as an output is excluded from

the interrupt-on-change comparison). The input pins (of

RB7:RB4) are compared with the value latched on the

last read of PORTB. The “mismatch” outputs of

RB7:RB4 are OR’d together to generate the RB Port

Change Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow flag bit RBIF to be cleared.

This interrupt-on-mismatch feature, together with soft-

ware configurable pull-ups on these four pins, allow

easy interface to a keypad and make it possible for

wake-up on key depression. Refer to the Embedded

Control Handbook, “Implementing Wake-up on Key

Stroke” (AN552).

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

RB0/INT is an external interrupt input pin and is config-

ured using the INTEDG bit (OPTION_REG<6>).

RB0/INT is discussed in detail in Section 13.5.1.

FIGURE 5-4:

BLOCK DIAGRAM OF

RB7:RB4 PINS

RBPU(2)

Data Bus

WR Port

Data Latch

DQ

CK

VDD

P

Weak

Pull-up

I/O pin(1)

TRIS Latch

DQ

WR TRIS

CK

TTL

Input

Buffer

ST

Buffer

RD TRIS

Latch

QD

Set RBIF

RD Port

EN

Q1

From other

RB7:RB4 pins

QD

EN

RB7:RB6 in Serial Programming mode

RD Port

Q3

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (OPTION_REG<7>).

 2000 Microchip Technology Inc.

DS30605C-page 31

Share Link: