PIC16LCR64AT-04I/SO 查看數據表（PDF） - Microchip Technology

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PIC16LCR64AT-04I/SO

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

4.2.2.7 PIR2 REGISTER

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

This register contains the CCP2 interrupt flag bit.

.

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

FIGURE 4-21: PIR2 REGISTER (ADDRESS 0Dh)

U-0

—

bit7

bit 7-1:

bit 0:

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

—

—

—

—

—

—

CCP2IF

bit0

Unimplemented: Read as '0'

CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to

enabling an interrupt.

DS30234D-page 46

© 1997 Microchip Technology Inc.

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