PIC16C62B/72A
TABLE 10-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
62B 72A
N/A
N/A
N/A
TMR0
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
62B 72A
0000h
0000h
PC + 1(2)
STATUS
62B 72A
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA(4)
62B 72A
--0x 0000
--0u 0000
--uu uuuu
PORTB(5)
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC(5)
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
62B 72A
---0 0000
---0 0000
---u uuuu
INTCON
62B 72A
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
62B 72A
62B 72A
---- 0000
-0-- 0000
---- 0000
-0-- 0000
---- uuuu(1)
-u-- uuuu(1)
TMR1L
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
62B 72A
--00 0000
--uu uuuu
--uu uuuu
TMR2
62B 72A
0000 0000
0000 0000
uuuu uuuu
T2CON
62B 72A
-000 0000
-000 0000
-uuu uuuu
SSPBUF
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
62B 72A
0000 0000
0000 0000
uuuu uuuu
CCPR1L
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
62B 72A
--00 0000
--00 0000
--uu uuuu
ADRES
62B 72A
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
62B 72A
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
62B 72A
1111 1111
1111 1111
uuuu uuuu
TRISA
62B 72A
--11 1111
--11 1111
--uu uuuu
TRISB
62B 72A
1111 1111
1111 1111
uuuu uuuu
TRISC
62B 72A
1111 1111
1111 1111
uuuu uuuu
PIE1
62B 72A
62B 72A
---- 0000
-0-- 0000
---- 0000
-0-- 0000
---- uuuu
-u-- uuuu
PCON
62B 72A
---- --0q
---- --uq
---- --uq
PR2
62B 72A
1111 1111
1111 1111
1111 1111
SSPADD
62B 72A
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
62B 72A
0000 0000
0000 0000
uuuu uuuu
ADCON1
62B 72A
---- -000
---- -000
---- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 10-5 for reset value for specific condition.
4: On any device reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
© 1999 Microchip Technology Inc.
Preliminary
DS35008B-page 61